I need you to complete the circuit design in quartus, that follows the Requirements and constraints
1. You are permitted to modify only the Verilog files block0.v, block1.v, block2.v and block3.v, the ROM contents file
(rom.txt) and waveform files. You must not modify any other file or schematic in the project. You must not add or
remove any files, other than waveform files, to the project. Any additional modules that you might need to create to
implement each functional block should be included in the corresponding block#.v file.
(rom.txt) and waveform files. You must not modify any other file or schematic in the project. You must not add or
remove any files, other than waveform files, to the project. Any additional modules that you might need to create to
implement each functional block should be included in the corresponding block#.v file.
2. You are not permitted to modify the port declaration of the block0, block1, block2 and block3 modules.
3. You must implement your design using structural and dataflow Verilog constructs (gate primitives, assign statements
with operators). You may not use dataflow arithmetic operators (e.g. assign F = A + B; or assign F = A – B)., or any
other operators listed on the “Other Dataflow Operators” slides.
with operators). You may not use dataflow arithmetic operators (e.g. assign F = A + B; or assign F = A – B)., or any
other operators listed on the “Other Dataflow Operators” slides.
4. You are not permitted to create any schematics or to use behavioral Verilog constructs (e.g., case statements, for
loops).
loops).
5. Your design must be completely combinational.
6. You must assign a unique 3-bit code to each operation.
7. Your rom.txt file must include the last four digits of your student ID number and the validation data described in the
Completion section below
Completion section below